Switching Activity Reduction Using Scan Shift Operation

This paper presents BIST TPG (built in self test) for low power dissipation and high fault coverage a low hardware overhead test pattern generator (TPG) for scan-based built-in self-test (BIST) that can reduce switching activity in circuits under test (CUTs) during BIST and also achieve very high fault coverage with reasonable lengths of test sequences. The proposed BIST TPG subside transitions that occur at scan inputs during scan shift operations and hence reduces switching activity in the CUT. The proposed BIST is comprised of two TPGs: LT-RTPG and 3-weight WRBIST. Test patterns engender by the LT-RTPG detect easy-to-detect faults and test patterns generated by the 3-weight WRBIST detect faults that abide undetected after LT-RTPG patterns are applied. The proposed BIST TPG does not require modification of delegation logics, which can lead to performance degeneracy. The 3-weight weighted random BIST techniques to reduce test sequence lengths by improving detection probabilities of random pattern resistant faults. A forthright solution is to reduce the speed of the test clock during scan shift operations. However, since most test application time of scan-based BIST is expend for scan shift operations, this will increase test application time by about a factor of if scan flip-flops are clocked at speed during scan shift operations. The proposed BIST can suggestive reduce switching activity during BIST while achieving 100% fault coverage .Larger reduction in switching activity is achieved in large circuits.